I also moved some of the waveforms around and updated the block diagram I was using so it would be easier to follow. Here is my test bench for generating a BPSK signal and providing gain values for the PI filter: That is pretty much the whole design, now I will finish up with simulation set up and results. I should also note that all the Adder/Subtracter blocks in Vivado are set to the Adding mode, not the subtracting mode. Regarding the integrator path, I handled the delay by making that adder synchronous (added a clock signal to it). Going off of that here is the reference design I using: PI Loop Filter Block Diagram. I have read several papers on what the appropriate design for this filter is some say it has to be a FIR LPF, some say it has to be an IIR LPF, some say it should be PID contol filter, but most say it has to be a proportional + integral(PI) filter.
Lastly, comes the loop filter, which I believe is the heart of the issue, but I will get into that in a bit. Here are the settings I used for the core: DDS Settings I don't have enough reputation on stack overflow for 9 screenshots so I will just say that the core is in phase increment streaming mode and phase offset is turned off. The DDS core will generate two tones that are 90 degrees out of phase which I use for the I/Q arms. Here is a screenshot of the IP core settings I was using as well as the frequency response: Low Pass Filter(LPF) Settingsįor the NCO, I used Xilinx's DDS core to act as a phase accumulator and SIN/COS LUT. I used python to come up with good filter taps. The cutoff frequency just needs to be small enough to eliminate the summation of the NCO frequency and the BPSK frequency, while not eliminating the difference between these frequencies. I originally tried to make this all in VHDL code, but because I ended up using almost entirely IP cores, I decided to make it in Vivado's IP integrator: Vivado IP Integrator Block Diagramįrom my research online, I found the low pass filter for the I and Q arm can be a simple SRRC filter using a FIR design. Here is the reference block diagram I have been using to design the loop: Costas Loop Block Diagram
I am currently trying to implement a Costas Loop in order to demodulate a BPSK signal.